1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2009, zarlink semiconductor inc. all rights reserved. features ? supports the requirements of itu-t g.8262 for synchronous ethernet equipment slave clocks (eec option 1 and 2) ? supports the requirements of telcordia gr-1244 stratum 3 and gr-253, itu-t g.812, g.813 ? supports itu-t g.823, g.824 and g.8261 for 2048 kbit/s and 1544 kbit/s interfaces ? meets the sonet/sdh jitter generation requirements up to oc-48/stm-16 ? synchronizes to telecom reference clocks (2 khz, n*8 khz up to 77.76 mhz, 155.52 mhz) or to ethernet reference clocks (25 mhz, 50 mhz, 62.5 mhz, 125 mhz) ? generates standard sonet/sdh clock rates (e.g., 19.44 mhz, 38.88 mhz, 77.76 mhz, 155.52 mhz, 622.08 mhz) or ethernet clock rates (e.g., 25 mhz, 50 mhz, 125 mhz, 156.25 mhz, 312.5 mhz) for synchronizing gigabit ethernet phys ? programmable output synthesizer generates telecom clock frequencies from any multiple of 8 khz up to 100 mhz ? generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency ? internal state machine automatically controls mode of operation (free-run, locked, holdover) ? flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities ? provides automatic reference switching and holdover during loss of reference input ? supports master/slave configuration and dynamic input to output delay compensation for advancedtca tm ? configurable input to output delay and output to output phase alignment applications ? itu-t g.8262 system timing cards which support 1 gbe interfaces ? telcordia gr-253 carrier grade sonet/sdh stratum 3 system timing cards february 2009 figure 1 - functional block diagram apll_clk sonet/ ethernet apll dpll ref sync /n1 /n2 i 2 c/spi jtag osco osci lock mode hold ref0 ref1 ref2 sync0 sync1 sync2 diff p_clk p_fp programmable synthesizer n*8khz ZL30142 synce sonet/sdh g.8262/stratum 3 system synchronizer short form data sheet ordering information ZL30142ggg 64 pin cabga trays ZL30142ggg2 64 pin cabga* trays *pb free tin/silver/copper -40 o c to +85 o c
ZL30142 short form data sheet 2 zarlink semiconductor inc. 1.0 high level overview the ZL30142 sonet/sdh/gbe stratum 3 system synchronizer and sets device is a highly integrated device that provides all of the func tionality that is required fo r a central timing card in carr ier grade network equipment. the basic functions of a central timing card include: ? input reference monitoring for both frequency accuracy and phase irregularities ? automatic input reference selection ? support of both external timing and line timing modes ? hitless reference switching ? wander and jitter filtering ? master/slave crossover for minimizing phase alignment between redundant timing cards ? independent derived output timing path for support of the sets functionality in a typical application, the main timing path uses the dpll to synchronize to either an ex ternal bits source or to a recovered line timed source. the dpll monitors the re ferences and automatically selects the best available reference based on configurable priority and revertive proper ties. the dpll provides the wander filtering function and the p0 synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards with a common timing reference. figure 2 - typical application of the ZL30142 line recovered tim ing system tim ing bus 19.44 m hz 19.44 m hz 19.44 m hz zl30146 apll tx dpll a b 622.08 m hz oc-192 line card phy 8 khz telecom backplane zl30146 apll tx dpll a b 156.25 m hz 10gbe line card phy 25 m hz s 19.44 m hz p central tim ing card bits a p s ps a dpll central tim ing card bits b ps p s b dpll xover ZL30142 prog synth rx dpll prog synth rx dpll ZL30142
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